1. Field of the Invention
The present invention relates to a polishing method and apparatus, and more particularly to a polishing method and apparatus for polishing and planarizing an object to be polished (substrate) such as a semiconductor wafer.
2. Description of the Related Art
In recent years, high integration and high density in semiconductor device demands smaller and smaller wiring patterns or interconnections and also more and more interconnection layers. Multilayer interconnections in smaller circuits result in greater steps which reflect surface irregularities on lower interconnection layers. An increase in the number of interconnection layers makes film coating performance (step coverage) poor over stepped configurations of thin films. Therefore, better multilayer interconnections need to have the improved step coverage and proper surface planarization. Further, since the depth of focus of a photolithographic optical system is smaller with miniaturization of a photolithographic process, a surface of the semiconductor device needs to be planarized such that irregular steps on the surface of the semiconductor device will fall within the depth of focus.
Thus, in a manufacturing process of a semiconductor device, it increasingly becomes important to planarize a surface of the semiconductor device. One of the most important planarizing technologies is chemical mechanical polishing (CMP). In the chemical mechanical polishing, while a polishing liquid containing abrasive particles such as silica (SiO2) therein is supplied onto a polishing surface such as a polishing pad, a substrate such as a semiconductor wafer is brought into sliding contact with the polishing surface and polished using the polishing apparatus.
In forming the above mentioned multilayer interconnections, there has been performed a process in which grooves for interconnections having a predetermined pattern are formed in an insulating layer (dielectric material) on a substrate, the substrate is then dipped in a plating solution to plate the substrate with copper (Cu), for example, by an electroless plating or an electrolytic plating, and then unnecessary portions of a copper layer is selectively removed from the substrate by a CMP process, while leaving only the copper layer in the grooves for interconnections. In this case, if the substrate is insufficiently polished to leave the copper layer on the insulating layer (oxide film), then the circuits would not be separated from each other, but short-circuited. Conversely, if the copper layer in the interconnection grooves is excessively polished away together with the insulating layer, then the resistance of the circuits on the substrate would be so increased that the entirety of the semiconductor substrate might possibly need to be discarded, resulting in a large loss. This holds true for the cases in which other metal films such as aluminum layer are formed, and then polished by the CMP process.
The polishing apparatus which performs the above-mentioned CMP process includes a polishing table having a polishing surface formed by a polishing pad, and a substrate holding device, which is referred to as a top ring or a polishing head, for holding a semiconductor wafer (substrate). When a semiconductor wafer is polished with such a polishing apparatus, the semiconductor wafer is held and pressed against the polishing surface under a predetermined pressure by the substrate holding device. At this time, the polishing table and the substrate holding device are moved relative to each other to bring the semiconductor wafer into sliding contact with the polishing surface, so that the surface of the semiconductor wafer is polished to a flat mirror finish.
Such polishing apparatuses include a type of polishing apparatus which has a pressure chamber formed by an elastic membrane at the lower portion of the substrate holding device and supplies the pressure chamber with a fluid such as air to press the semiconductor wafer against the polishing substrate under a fluid pressure through the elastic membrane, as disclosed in Japanese laid-open patent publication No. 2006-255851, and a type of polishing apparatus which has a holding surface having rigidity formed by ceramics or the like at the lower portion of the substrate holding device and applies a force to the holding surface by an air cylinder or the like to press the semiconductor wafer against the polishing surface.